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Micrel, Inc.

KSZ8841-PMQL

October 2007

M9999-100407-1.5

Host Communication

The descriptor lists and data buffers, collectively called the host communication, manage the actions and status related

to buffer management. Commands and signals that control the functional operation of the KSZ8841-PMQL are also

described.

The KSZ8841-PMQL and the driver communicate through the two data structures: Command and status registers

(CSRs) and Descriptor Lists and Data Buffers.

Note: All unused bits of the data structure in this section are reserved and should be written by the driver as zeros.

Host Communication Descriptor Lists and Data Buffers

The KSZ8841-PMQL transfers received data frames to the receive buffer in host memory and transmits data from the

transmit buffers in host memory. Descriptors that reside in the host memory act as pointers to these buffers.

There are two descriptor lists (one for receive and one for transmit) for the MAC DMA. The base address of each list is

written in the TDLB register and in the RDLB register, respectively. A descriptor list is forward linked. The last descriptor

may point back to the first entry to create a ring structure. Descriptors are chained by setting the next address to the

next buffer in both receive and transmit descriptors.

The descriptor lists reside in the host physical memory address space. Each pointer points to one buffer and the

second pointer points to the next descriptor. This enables the greatest flexibility for the host to chain any data buffers

with discontinuous memory location. This eliminates processor-intensive tasks such as memory copying from the host

to memory.

A data buffer contains either an entire frame or part of a frame, but it cannot exceed a single frame. Buffers contain only

data; and buffer status is maintained in the descriptor. Data chaining refers to frames that span multiple data buffers.

Data chaining can be enabled or disabled. Data buffers reside in host physical memory space.

Receive Descriptors (RDES0-RDES3)

Receive descriptor and buffer addresses must be Word aligned. Each receive descriptor provides one frame buffer, one

byte count field, and control and status bits.

The following table shows the RDES0 register bit fields.

Bit

Description

OWN Own Bit

When set, indicates that the descriptor is owned by the KSZ8841-PMQL.

When reset, indicates that the descriptor is owned by the host. The KSZ8841-PMQL clears

this bit either when it completes the frame reception or when the buffers that are associated

with this descriptor are full.

FS First Descriptor

When set, indicates that this descriptor contains the first buffer of a frame.

If the buffer size of the first buffer is 0, the next buffer contains the beginning of the frame.

LS Last Descriptor

When set, indicates that the buffer pointed by this descriptor is the last buffer of the frame.

IPE IP Checksum Error

When set, indicates that the received frame is an IP packet and its IP checksum field does

not match.

This bit is valid only when last descriptor is set.

TCPE TCP Checksum Error

When set, indicates that the received frame is a TCP/IP packet and its TCP checksum field

does not match.

This bit is valid only when last descriptor is set.

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